ixgbe and GitHub
79d61896d3
ggml-cpu: add ggml_thread_cpu_relax with Zihintpause support ( #17784 )
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* ggml-cpu: add ggml_thread_cpu_relax with Zihintpause support
Signed-off-by: Wang Yang <yangwang@iscas.ac.cn >
* cmake: enable RISC-V zihintpause extension for Spacemit builds
* readme : add ZIHINTPAUSE support for RISC-V
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Signed-off-by: Wang Yang <yangwang@iscas.ac.cn >
2025-12-08 10:41:34 +02:00
ixgbe and GitHub
f698a79c63
ggml: replace hwcap with riscv_hwprobe for RVV detection ( #17567 )
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Signed-off-by: Wang Yang <yangwang@iscas.ac.cn >
2025-11-29 14:56:31 +02:00
ixgbe and GitHub
5f55c385cb
ggml: add RISC-V cpu-feats ( #17461 )
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* ggml: add RISC-V cpu-feats
Signed-off-by: Wang Yang <yangwang@iscas.ac.cn >
* fix comment[1]
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Signed-off-by: Wang Yang <yangwang@iscas.ac.cn >
2025-11-24 13:07:14 +02:00
ixgbe and GitHub
5be353ec4a
ggml-cpu:add RISC-V RVV (Zvfh) optimization for FP16 vector scaling ( #17314 )
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* ggml-cpu:add RISC-V RVV (Zvfh) optimization for FP16 vector scaling
Signed-off-by: Wang Yang <yangwang@iscas.ac.cn >
* fix comment
* fix comment 2
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Signed-off-by: Wang Yang <yangwang@iscas.ac.cn >
2025-11-20 08:09:18 +02:00
ixgbe and GitHub
307772fcda
readme : add RVV,ZVFH,ZFH,ZICBOP support for RISC-V ( #17259 )
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Signed-off-by: Wang Yang <yangwang@iscas.ac.cn >
2025-11-14 09:12:56 +02:00
ixgbe and GitHub
1215dde7b0
ggml-cpu : add RISC-V vector intrinsic support for silu and cvar operations ( #17227 )
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Signed-off-by: Wang Yang <yangwang@iscas.ac.cn >
2025-11-13 13:13:32 +01:00
ixgbe and GitHub
ca4844062b
ggml-cpu : add RISC-V RVV (Zvfh) optimization for FP16 to FP32 conversion ( #17161 )
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Signed-off-by: Wang Yang <yangwang@iscas.ac.cn >
2025-11-11 13:41:51 +02:00
