 ixgbeandGitHub
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f698a79c63
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ggml: replace hwcap with riscv_hwprobe for RVV detection (#17567)
Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
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2025-11-29 14:56:31 +02:00 |
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ixgbeandGitHub
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5f55c385cb
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ggml: add RISC-V cpu-feats (#17461)
* ggml: add RISC-V cpu-feats
Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
* fix comment[1]
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Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
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2025-11-24 13:07:14 +02:00 |
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ixgbeandGitHub
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5be353ec4a
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ggml-cpu:add RISC-V RVV (Zvfh) optimization for FP16 vector scaling (#17314)
* ggml-cpu:add RISC-V RVV (Zvfh) optimization for FP16 vector scaling
Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
* fix comment
* fix comment 2
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Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
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2025-11-20 08:09:18 +02:00 |
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ixgbeandGitHub
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307772fcda
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readme : add RVV,ZVFH,ZFH,ZICBOP support for RISC-V (#17259)
Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
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2025-11-14 09:12:56 +02:00 |
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ixgbeandGitHub
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1215dde7b0
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ggml-cpu : add RISC-V vector intrinsic support for silu and cvar operations (#17227)
Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
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2025-11-13 13:13:32 +01:00 |
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ixgbeandGitHub
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ca4844062b
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ggml-cpu : add RISC-V RVV (Zvfh) optimization for FP16 to FP32 conversion (#17161)
Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
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2025-11-11 13:41:51 +02:00 |
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