nikola/llama_cpp
1
0
Fork 0
Code Issues Pull Requests Actions 21 Packages Projects Releases Wiki Activity
9,897 Commits 1 Branch 0 Tags
nik
Commit Graph
8 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
ixgbeGitHubGeorgi Gerganov
 		51604435e8 ggml-cpu : fix RISC-V Q4_0 repack select and RVV feature reporting (#17951) 
* ggml-cpu:fix RISC-V Q4_0 repack select and RVV feature reporting

Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>

* using the name VLEN instead of CNT

* Update ggml/include/ggml-cpu.h

---------

Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
Co-authored-by: Georgi Gerganov <ggerganov@gmail.com>
 2025-12-12 16:26:03 +02:00
ixgbeandGitHub 79d61896d3 ggml-cpu: add ggml_thread_cpu_relax with Zihintpause support (#17784) 
* ggml-cpu: add ggml_thread_cpu_relax with Zihintpause support

Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>

* cmake: enable RISC-V zihintpause extension for Spacemit builds

* readme : add ZIHINTPAUSE support for RISC-V

---------

Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
 2025-12-08 10:41:34 +02:00
ixgbeandGitHub f698a79c63 ggml: replace hwcap with riscv_hwprobe for RVV detection (#17567) 
Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
 2025-11-29 14:56:31 +02:00
ixgbeandGitHub 5f55c385cb ggml: add RISC-V cpu-feats (#17461) 
* ggml: add RISC-V cpu-feats

Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>

* fix comment[1]

---------

Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
 2025-11-24 13:07:14 +02:00
ixgbeandGitHub 5be353ec4a ggml-cpu:add RISC-V RVV (Zvfh) optimization for FP16 vector scaling (#17314) 
* ggml-cpu:add RISC-V RVV (Zvfh) optimization for FP16 vector scaling

Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>

* fix comment

* fix comment 2

---------

Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
 2025-11-20 08:09:18 +02:00
ixgbeandGitHub 307772fcda readme : add RVV,ZVFH,ZFH,ZICBOP support for RISC-V (#17259) 
Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
 2025-11-14 09:12:56 +02:00
ixgbeandGitHub 1215dde7b0 ggml-cpu : add RISC-V vector intrinsic support for silu and cvar operations (#17227) 
Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
 2025-11-13 13:13:32 +01:00
ixgbeandGitHub ca4844062b ggml-cpu : add RISC-V RVV (Zvfh) optimization for FP16 to FP32 conversion (#17161) 
Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
 2025-11-11 13:41:51 +02:00