fbd441c379
* hexagon : add cumsum op support * hexagon: enable dma for cumsum op * Fix line-ending --------- Co-authored-by: Max Krasnyansky <maxk@qti.qualcomm.com>
268 lines
10 KiB
C
268 lines
10 KiB
C
#pragma clang diagnostic ignored "-Wunused-variable"
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#pragma clang diagnostic ignored "-Wunused-function"
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#pragma clang diagnostic ignored "-Wunused-but-set-variable"
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#include <HAP_farf.h>
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#include <HAP_perf.h>
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#define GGML_COMMON_DECL_C
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#include "ggml-common.h"
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#include "htp-ctx.h"
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#include "htp-ops.h"
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#include "hvx-types.h"
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#include "hvx-utils.h"
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#include "hex-dma.h"
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#define htp_cumsum_tensors_preamble \
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struct htp_tensor * restrict src0 = &octx->src0; \
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struct htp_tensor * restrict dst = &octx->dst; \
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\
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const uint32_t ne00 = src0->ne[0]; \
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const uint32_t ne01 = src0->ne[1]; \
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const uint32_t ne02 = src0->ne[2]; \
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const uint32_t ne03 = src0->ne[3]; \
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\
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const uint32_t ne0 = dst->ne[0]; \
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const uint32_t ne1 = dst->ne[1]; \
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const uint32_t ne2 = dst->ne[2]; \
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const uint32_t ne3 = dst->ne[3]; \
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\
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const uint32_t nb00 = src0->nb[0]; \
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const uint32_t nb01 = src0->nb[1]; \
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const uint32_t nb02 = src0->nb[2]; \
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const uint32_t nb03 = src0->nb[3]; \
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\
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const uint32_t nb0 = dst->nb[0]; \
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const uint32_t nb1 = dst->nb[1]; \
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const uint32_t nb2 = dst->nb[2]; \
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const uint32_t nb3 = dst->nb[3];
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struct htp_cumsum_context {
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struct htp_ops_context * octx;
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size_t src_row_size;
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size_t dst_row_size;
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size_t src_row_size_aligned;
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size_t dst_row_size_aligned;
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uint32_t rows_per_thread;
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uint32_t total_rows;
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};
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#define htp_cumsum_preamble \
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struct htp_cumsum_context * cctx = (struct htp_cumsum_context *) data; \
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struct htp_ops_context * octx = cctx->octx; \
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htp_cumsum_tensors_preamble; \
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dma_queue * dma_queue = octx->ctx->dma[ith];
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// ---------------------------------------------------------------------------
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// HVX prefix scan helpers
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// ---------------------------------------------------------------------------
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#if __HVX_ARCH__ > 75
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static inline HVX_Vector hvx_cumsum_vadd(HVX_Vector a, HVX_Vector b) {
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return Q6_Vsf_vadd_VsfVsf(a, b);
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}
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#else
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static inline HVX_Vector hvx_cumsum_vadd(HVX_Vector a, HVX_Vector b) {
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return Q6_Vsf_equals_Vqf32(Q6_Vqf32_vadd_VsfVsf(a, b));
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}
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#endif // __HVX_ARCH__ > 75
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static inline HVX_Vector hvx_prefix_scan_f32(HVX_Vector v, HVX_Vector carry_in) {
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const HVX_Vector zero = Q6_V_vsplat_R(0);
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v = hvx_cumsum_vadd(v, Q6_V_vlalign_VVR(v, zero, 4));
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v = hvx_cumsum_vadd(v, Q6_V_vlalign_VVR(v, zero, 8));
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v = hvx_cumsum_vadd(v, Q6_V_vlalign_VVR(v, zero, 16));
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v = hvx_cumsum_vadd(v, Q6_V_vlalign_VVR(v, zero, 32));
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v = hvx_cumsum_vadd(v, Q6_V_vlalign_VVR(v, zero, 64));
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v = hvx_cumsum_vadd(v, carry_in);
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return v;
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}
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static inline HVX_Vector hvx_splat_last_f32(HVX_Vector v) {
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return hvx_vec_repl4(Q6_V_vror_VR(v, 124));
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}
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static inline void hvx_cumsum_row_f32(const float * restrict src, float * restrict dst, uint32_t n) {
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const uint32_t nvec = n / VLEN_FP32;
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const uint32_t nloe = n % VLEN_FP32;
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HVX_Vector carry = Q6_V_vsplat_R(0);
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for (uint32_t i = 0; i < nvec; i++) {
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HVX_Vector v = *((const HVX_UVector *) (src + i * VLEN_FP32));
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v = hvx_prefix_scan_f32(v, carry);
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hvx_vec_store_u(dst + i * VLEN_FP32, VLEN, v);
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carry = hvx_splat_last_f32(v);
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}
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if (nloe) {
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float acc = hvx_vec_get_f32(carry);
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const float * src_tail = src + nvec * VLEN_FP32;
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float * dst_tail = dst + nvec * VLEN_FP32;
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for (uint32_t i = 0; i < nloe; i++) {
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acc += src_tail[i];
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dst_tail[i] = acc;
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}
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}
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}
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// ---------------------------------------------------------------------------
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// Per thread worker: Double-buffered DMA
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// ---------------------------------------------------------------------------
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static void cumsum_thread_f32_dma(unsigned int nth, unsigned int ith, void * data) {
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htp_cumsum_preamble;
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uint64_t t1, t2;
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t1 = HAP_perf_get_qtimer_count();
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const uint32_t ir0 = cctx->rows_per_thread * ith;
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const uint32_t ir1 = MIN(ir0 + cctx->rows_per_thread, cctx->total_rows);
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if (ir0 >= ir1) {
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return;
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}
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const size_t src_row_size = cctx->src_row_size;
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const size_t dst_row_size = cctx->dst_row_size;
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const size_t src_row_size_aligned = cctx->src_row_size_aligned;
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const size_t dst_row_size_aligned = cctx->dst_row_size_aligned;
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const uint8_t * src_data = (const uint8_t *) src0->data;
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uint8_t * dst_data = (uint8_t *) dst->data;
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uint8_t * src_spad = octx->src0_spad.data + (ith * src_row_size_aligned * 2);
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uint8_t * dst_spad = octx->dst_spad.data + (ith * dst_row_size_aligned * 2);
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for (uint32_t ir = ir0, spad_idx = 0; ir < ir1 && spad_idx < 2; ir++, spad_idx++) {
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// Dummy dst writeback to establish queue ordering
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dma_queue_push_vtcm_to_ddr(dma_queue,
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dma_make_ptr(dst_data, dst_spad + (spad_idx * dst_row_size_aligned)),
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dst_row_size, dst_row_size_aligned, 0);
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dma_queue_push_ddr_to_vtcm(dma_queue,
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dma_make_ptr(src_spad + (spad_idx * src_row_size_aligned),
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src_data + (ir * src_row_size)),
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src_row_size_aligned, src_row_size, 1);
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}
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for (uint32_t ir = ir0; ir < ir1; ir++) {
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float * dst_spad_row = (float *) dma_queue_pop(dma_queue).src;
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float * src_spad_row = (float *) dma_queue_pop(dma_queue).dst;
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hvx_cumsum_row_f32(src_spad_row, dst_spad_row, ne00);
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dma_queue_push_vtcm_to_ddr(dma_queue,
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dma_make_ptr(dst_data + (ir * dst_row_size), (uint8_t *) dst_spad_row),
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dst_row_size, dst_row_size_aligned, 1);
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const uint32_t next_row = ir + 2;
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if (next_row < ir1) {
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dma_queue_push_ddr_to_vtcm(dma_queue,
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dma_make_ptr((uint8_t *) src_spad_row, src_data + (next_row * src_row_size)),
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src_row_size_aligned, src_row_size, 1);
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}
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}
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dma_queue_flush(dma_queue);
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t2 = HAP_perf_get_qtimer_count();
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FARF(HIGH, "cumsum-f32-dma %d/%d: %ux%ux%ux%u (%u:%u) -> %ux%ux%ux%u usec %u\n",
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ith, nth, src0->ne[0], src0->ne[1], src0->ne[2], src0->ne[3], ir0, ir1,
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dst->ne[0], dst->ne[1], dst->ne[2], dst->ne[3],
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(unsigned) HAP_perf_qtimer_count_to_us(t2 - t1));
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}
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// ---------------------------------------------------------------------------
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// Per thread worker: Direct HVX (no DMA)
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// ---------------------------------------------------------------------------
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static void cumsum_thread_f32(unsigned int nth, unsigned int ith, void * data) {
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htp_cumsum_preamble;
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uint64_t t1, t2;
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t1 = HAP_perf_get_qtimer_count();
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const uint8_t * src_data = (const uint8_t *) src0->data;
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uint8_t * dst_data = (uint8_t *) dst->data;
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const uint32_t ir0 = cctx->rows_per_thread * ith;
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const uint32_t ir1 = MIN(ir0 + cctx->rows_per_thread, cctx->total_rows);
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for (uint32_t ir = ir0; ir < ir1; ir++) {
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const float * restrict src_row = (const float *) (src_data + ir * cctx->src_row_size);
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float * restrict dst_row = (float *) (dst_data + ir * cctx->dst_row_size);
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hvx_cumsum_row_f32(src_row, dst_row, ne00);
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}
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t2 = HAP_perf_get_qtimer_count();
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FARF(HIGH, "cumsum-f32 %d/%d: %ux%ux%ux%u (%u:%u) -> %ux%ux%ux%u usec %u\n",
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ith, nth, src0->ne[0], src0->ne[1], src0->ne[2], src0->ne[3], ir0, ir1,
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dst->ne[0], dst->ne[1], dst->ne[2], dst->ne[3],
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(unsigned) HAP_perf_qtimer_count_to_us(t2 - t1));
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}
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int op_cumsum_f32(struct htp_ops_context * octx) {
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const struct htp_tensor * src0 = &octx->src0;
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const struct htp_tensor * dst = &octx->dst;
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if (octx->flags & HTP_OPFLAGS_SKIP_COMPUTE) {
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return HTP_STATUS_OK;
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}
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const uint32_t total_rows = src0->ne[1] * src0->ne[2] * src0->ne[3];
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const uint32_t n_threads = MIN(octx->n_threads, total_rows);
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const size_t src_row_size = src0->nb[1];
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const size_t dst_row_size = dst->nb[1];
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const size_t src_row_size_aligned = hex_round_up(src_row_size, VLEN);
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const size_t dst_row_size_aligned = hex_round_up(dst_row_size, VLEN);
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// 2 ping-pong buffers per thread for src and dst
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const size_t spad_per_thread = 2 * (src_row_size_aligned + dst_row_size_aligned);
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octx->src0_spad.size_per_thread = src_row_size_aligned * 2;
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octx->dst_spad.size_per_thread = dst_row_size_aligned * 2;
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octx->src0_spad.size = n_threads * octx->src0_spad.size_per_thread;
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octx->dst_spad.size = n_threads * octx->dst_spad.size_per_thread;
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octx->src0_spad.data = octx->ctx->vtcm_base;
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octx->dst_spad.data = octx->src0_spad.data + octx->src0_spad.size;
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struct htp_cumsum_context cctx = {
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.octx = octx,
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.src_row_size = src_row_size,
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.dst_row_size = dst_row_size,
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.src_row_size_aligned = src_row_size_aligned,
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.dst_row_size_aligned = dst_row_size_aligned,
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.rows_per_thread = (total_rows + n_threads - 1) / n_threads,
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.total_rows = total_rows,
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};
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if (octx->ctx->vtcm_size < spad_per_thread * n_threads) {
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worker_pool_run_func(octx->ctx->worker_pool, cumsum_thread_f32, &cctx, n_threads);
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} else {
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worker_pool_run_func(octx->ctx->worker_pool, cumsum_thread_f32_dma, &cctx, n_threads);
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}
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return HTP_STATUS_OK;
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}
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int op_cumsum(struct htp_ops_context * octx) {
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int err = HTP_STATUS_OK;
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struct htp_tensor * dst = &octx->dst;
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switch (dst->type) {
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case HTP_TYPE_F32:
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err = op_cumsum_f32(octx);
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break;
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default:
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err = HTP_STATUS_NO_SUPPORT;
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break;
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}
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return err;
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}
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