CUDA: tune GLM 4.7 Flash FA kernel selection logic (DGX Spark) (#19142)
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@@ -53,6 +53,7 @@
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// While BW spans CC 1000, 1100 & 1200, we are integrating Tensor Core instructions available to 1200 family, see
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// While BW spans CC 1000, 1100 & 1200, we are integrating Tensor Core instructions available to 1200 family, see
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// https://docs.nvidia.com/cutlass/media/docs/cpp/blackwell_functionality.html#blackwell-sm120-gemms
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// https://docs.nvidia.com/cutlass/media/docs/cpp/blackwell_functionality.html#blackwell-sm120-gemms
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#define GGML_CUDA_CC_BLACKWELL 1200
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#define GGML_CUDA_CC_BLACKWELL 1200
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#define GGML_CUDA_CC_DGX_SPARK 1210
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#define GGML_CUDA_CC_RUBIN 1300
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#define GGML_CUDA_CC_RUBIN 1300
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#define GGML_CUDA_CC_OFFSET_AMD 0x1000000
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#define GGML_CUDA_CC_OFFSET_AMD 0x1000000
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#define GGML_CUDA_CC_OFFSET_MTHREADS 0x0100000
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#define GGML_CUDA_CC_OFFSET_MTHREADS 0x0100000
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@@ -147,6 +147,14 @@ static void ggml_cuda_flash_attn_ext_mma_f16(ggml_backend_cuda_context & ctx, gg
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GGML_ASSERT(Q->ne[2] % K->ne[2] == 0);
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GGML_ASSERT(Q->ne[2] % K->ne[2] == 0);
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const int gqa_ratio = Q->ne[2] / K->ne[2];
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const int gqa_ratio = Q->ne[2] / K->ne[2];
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if (gqa_ratio == 20) { // GLM 4.7 Flash
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if (gqa_ratio == 20) { // GLM 4.7 Flash
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if (cc >= GGML_CUDA_CC_DGX_SPARK) {
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if (Q->ne[1] <= 8) {
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols1<576, 512, 16>(ctx, dst);
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break;
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}
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols1<576, 512, 4>(ctx, dst);
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break;
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}
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if (cc >= GGML_CUDA_CC_BLACKWELL) {
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if (cc >= GGML_CUDA_CC_BLACKWELL) {
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if (Q->ne[1] <= 4 && K->ne[1] >= 65536) {
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if (Q->ne[1] <= 4 && K->ne[1] >= 65536) {
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols1<576, 512, 16>(ctx, dst);
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols1<576, 512, 16>(ctx, dst);
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