CUDA: generalized (mma) FA, add Volta support (#17505)
* CUDA: generalized (mma) FA, add Volta support * use struct for MMA FA kernel config --------- Co-authored-by: Aman Gupta <aman>
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co-authored by
Aman Gupta <aman>
parent
190c4838bd
commit
2e1c9cd814
@@ -501,6 +501,7 @@ static __device__ __forceinline__ void flash_attn_tile_iter(
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const half2 * const __restrict__ K_h2,
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const half2 * const __restrict__ V_h2,
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const half * const __restrict__ mask,
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const uint3 ne01,
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const float logit_softcap,
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const float slope,
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T_KQ * const KQ,
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@@ -512,7 +513,8 @@ static __device__ __forceinline__ void flash_attn_tile_iter(
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float * const KQ_sum,
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T_acc * const VKQ,
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const int k_VKQ_0,
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const int k_VKQ_max) {
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const int k_VKQ_max,
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const int col_Q_0) {
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constexpr int cpy_nb = ggml_cuda_get_max_cpy_bytes();
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constexpr int cpy_ne = cpy_nb / 4;
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@@ -556,7 +558,7 @@ static __device__ __forceinline__ void flash_attn_tile_iter(
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// Apply logit softcap + mask, update KQ_max:
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#pragma unroll
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for (int jc0 = 0; jc0 < cpw; ++jc0) {
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const int j = (jc0 + (threadIdx.y / np)*cpw)/ncols2;
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const int j = fastmodulo(col_Q_0 + (jc0 + (threadIdx.y / np)*cpw)/ncols2, ne01);
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#pragma unroll
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for (int i_KQ_0 = 0; i_KQ_0 < nbatch_fa; i_KQ_0 += np*warp_size) {
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@@ -736,7 +738,7 @@ static __global__ void flash_attn_tile(
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const float m1,
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const uint32_t n_head_log2,
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const float logit_softcap,
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const int32_t ne00, const int32_t ne01, const int32_t ne02, const int32_t ne03,
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const int32_t ne00, const uint3 ne01, const int32_t ne02, const int32_t ne03,
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const int32_t nb01, const int32_t nb02, const int32_t nb03,
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const int32_t ne10, const int32_t ne11, const int32_t ne12, const int32_t ne13,
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const int32_t nb11, const int32_t nb12, const int64_t nb13,
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@@ -781,11 +783,11 @@ static __global__ void flash_attn_tile(
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const int sequence = blockIdx.z / (ne02/ncols2);
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const int head0 = blockIdx.z*ncols2 - sequence*ne02; // == blockIdx.z % (ne02/ncols2)
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const int gqa_ratio = ne02 / ne12; // With grouped query attention there are > 1 Q matrices per K, V matrix.
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const float * Q_f = (const float *) (Q + nb03*sequence + nb02* head0 + nb01*col_Q_0);
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const float * Q_f = (const float *) (Q + nb03*sequence + nb02* head0);
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const half2 * K_h2 = (const half2 *) (K + nb13*sequence + nb12*(head0 / gqa_ratio));
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const half2 * V_h2 = (const half2 *) (V + nb23*sequence + nb22*(head0 / gqa_ratio)); // K and V have same shape
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const half * maskh = mask ? (const half *) (mask + nb33*(sequence % ne33) + nb31*col_Q_0) : nullptr;
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const half * maskh = mask ? (const half *) (mask + nb33*(sequence % ne33)) : nullptr;
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const int stride_K2 = nb11 / sizeof(half2);
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const int stride_V2 = nb21 / sizeof(half2);
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@@ -842,11 +844,9 @@ static __global__ void flash_attn_tile(
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for (int i0 = 0; i0 < DKQp; i0 += np*warp_size*cpy_ne_D) {
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if (i0 + np*warp_size*cpy_ne_D <= DKQ || i0 + (threadIdx.y % np)*(warp_size*cpy_ne_D) + threadIdx.x*cpy_ne_D < DKQ) {
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float tmp_f[cpy_ne_D] = {0.0f};
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if (ncols1 == 1 || col_Q_0 + j < ne01) {
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ggml_cuda_memcpy_1<sizeof(tmp_f)>
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(tmp_f, &Q_f[c*(nb02/sizeof(float)) + j*(nb01/sizeof(float))
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+ i0 + (threadIdx.y % np)*(warp_size*cpy_ne_D) + threadIdx.x*cpy_ne_D]);
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}
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ggml_cuda_memcpy_1<sizeof(tmp_f)>
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(tmp_f, &Q_f[c*(nb02/sizeof(float)) + fastmodulo(col_Q_0 + j, ne01)*(nb01/sizeof(float))
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+ i0 + (threadIdx.y % np)*(warp_size*cpy_ne_D) + threadIdx.x*cpy_ne_D]);
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#pragma unroll
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for (int i1 = 0; i1 < cpy_ne_D; ++i1) {
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@@ -881,23 +881,23 @@ static __global__ void flash_attn_tile(
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while (k_VKQ_0 < k_VKQ_max - nbatch_fa) {
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constexpr bool oob_check = false;
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flash_attn_tile_iter<warp_size, nwarps, ncols1, ncols2, DKQ, DV, nbatch_fa, nbatch_K, use_logit_softcap, oob_check>
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(Q_tmp, K_h2, V_h2, maskh, logit_softcap, slope, KQ, KV_tmp,
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stride_K2, stride_V2, stride_mask, KQ_max, KQ_sum, VKQ, k_VKQ_0, k_VKQ_max);
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(Q_tmp, K_h2, V_h2, maskh, ne01, logit_softcap, slope, KQ, KV_tmp,
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stride_K2, stride_V2, stride_mask, KQ_max, KQ_sum, VKQ, k_VKQ_0, k_VKQ_max, col_Q_0);
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k_VKQ_0 += gridDim.y*nbatch_fa;
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}
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if (k_VKQ_0 < k_VKQ_max) {
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constexpr bool oob_check = true;
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flash_attn_tile_iter<warp_size, nwarps, ncols1, ncols2, DKQ, DV, nbatch_fa, nbatch_K, use_logit_softcap, oob_check>
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(Q_tmp, K_h2, V_h2, maskh, logit_softcap, slope, KQ, KV_tmp,
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stride_K2, stride_V2, stride_mask, KQ_max, KQ_sum, VKQ, k_VKQ_0, k_VKQ_max);
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(Q_tmp, K_h2, V_h2, maskh, ne01, logit_softcap, slope, KQ, KV_tmp,
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stride_K2, stride_V2, stride_mask, KQ_max, KQ_sum, VKQ, k_VKQ_0, k_VKQ_max, col_Q_0);
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}
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} else {
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// Branch without out-of-bounds checks.
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for (int k_VKQ_0 = blockIdx.y*nbatch_fa; k_VKQ_0 < k_VKQ_max; k_VKQ_0 += gridDim.y*nbatch_fa) {
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constexpr bool oob_check = false;
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flash_attn_tile_iter<warp_size, nwarps, ncols1, ncols2, DKQ, DV, nbatch_fa, nbatch_K, use_logit_softcap, oob_check>
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(Q_tmp, K_h2, V_h2, maskh, logit_softcap, slope, KQ, KV_tmp,
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stride_K2, stride_V2, stride_mask, KQ_max, KQ_sum, VKQ, k_VKQ_0, k_VKQ_max);
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(Q_tmp, K_h2, V_h2, maskh, ne01, logit_softcap, slope, KQ, KV_tmp,
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stride_K2, stride_V2, stride_mask, KQ_max, KQ_sum, VKQ, k_VKQ_0, k_VKQ_max, col_Q_0);
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}
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}
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@@ -1010,13 +1010,13 @@ static __global__ void flash_attn_tile(
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const int j = jc / ncols2;
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const int c = jc % ncols2;
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if (ncols1 > 1 && col_Q_0 + j >= ne01) {
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if (ncols1 > 1 && col_Q_0 + j >= int(ne01.z)) {
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return;
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}
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const float scale = gridDim.y == 1 ? 1.0f/KQ_sum[jc0] : 1.0f;
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const int j_dst_unrolled = ((sequence*ne01 + col_Q_0 + j)*ne02 + head0 + c)*gridDim.y + blockIdx.y;
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const int j_dst_unrolled = ((sequence*int(ne01.z) + col_Q_0 + j)*ne02 + head0 + c)*gridDim.y + blockIdx.y;
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#ifdef FAST_FP16_AVAILABLE
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constexpr int cpy_ne_D = cpy_ne/2 < (DVp/2)/warp_size ? cpy_ne/2 : (DVp/2)/warp_size;
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