[SYCL] Add Q8_0 reorder optimization (~3x tg speedup on Intel Arc) (#21527)
Extend the existing reorder optimization to Q8_0. The reorder separates scale factors from weight data for coalesced memory access -- was implemented for Q4_0/Q4_K/Q6_K but Q8_0 was missing. On Arc Pro B70 (Xe2), Q8_0 tg goes from 4.88 to 15.24 t/s (3.1x) on Qwen3.5-27B. BW utilization: 21% -> 66%. The key fix beyond the kernels: Q8_0 was missing from the type check in ggml_backend_sycl_buffer_init_tensor() that allocates the extra struct carrying the reorder flag -- so the optimization was silently skipped. AI (Claude) was used to assist with root cause investigation and writing the kernel code. All code was human-reviewed and tested on real hardware. Fixes: #21517
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@@ -972,6 +972,103 @@ static void dequantize_mul_mat_vec_q5_1_sycl(const void *vx, const dfloat *y,
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}
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}
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static void dequantize_mul_mat_vec_q8_0_sycl_reorder(const void *vx, const dfloat *y,
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float *dst, const int ncols,
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const int nrows,
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dpct::queue_ptr stream) {
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GGML_ASSERT(ncols % GGML_SYCL_DMMV_X == 0);
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const int block_num_y = (nrows + GGML_SYCL_MMV_Y - 1) / GGML_SYCL_MMV_Y;
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const sycl::range<3> block_nums(1, 1, block_num_y);
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const sycl::range<3> block_dims(1, GGML_SYCL_MMV_Y, WARP_SIZE);
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{
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dpct::has_capability_or_fail(stream->get_device(),
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{sycl::aspect::fp16});
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stream->parallel_for(
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sycl::nd_range<3>(block_nums * block_dims, block_dims),
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[=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] {
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// Q8_0 reorder layout: [all qs (ncols*nrows bytes)][all d values]
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// Cannot reuse dequantize_mul_mat_vec_reorder template because it has
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// Q4_0-specific constants hardcoded (d_ptr offset and qs stride).
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const int row = item_ct1.get_group(2) * item_ct1.get_local_range(1) +
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item_ct1.get_local_id(1);
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if (row >= nrows) return;
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const int tid = item_ct1.get_local_id(2);
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const int iter_stride = 8*2*GGML_SYCL_DMMV_X;
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const int vals_per_iter = iter_stride / WARP_SIZE;
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const int ncols_left = ncols % (QK8_0*WARP_SIZE);
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const int ncols_align = ncols - ncols_left;
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#ifdef GGML_SYCL_F16
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sycl::half2 tmp = {0.0f, 0.0f};
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#else
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float tmp = 0.0f;
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#endif
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const char *d_ptr = (const char*)vx + ncols*nrows; // d after all qs
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int i = 0;
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for (i = 0; i < ncols_align; i += iter_stride) {
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const int col = i + vals_per_iter*tid;
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const int ib = (row*ncols + col)/QK8_0;
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const int iqs = col % QK8_0;
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#pragma unroll
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for (int j = 0; j < vals_per_iter; j += 2) {
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dfloat2 v;
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dequantize_q8_0_reorder((const void *)d_ptr, ib, (const void *)vx,
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ib * QK8_0 + iqs + j, v);
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#ifdef GGML_SYCL_F16
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dfloat2 t1{y[col + j + 0], y[col + j + 1]};
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tmp += v * t1;
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#else
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tmp += v.x() * y[col + j + 0];
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tmp += v.y() * y[col + j + 1];
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#endif
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}
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}
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// handle remaining columns
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for (; i < ncols; i += iter_stride) {
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if (tid >= ncols_left/QK8_0) continue;
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const int col = i + vals_per_iter*tid;
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const int ib = (row*ncols + col)/QK8_0;
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const int iqs = col % QK8_0;
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#pragma unroll
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for (int j = 0; j < vals_per_iter; j += 2) {
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dfloat2 v;
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dequantize_q8_0_reorder((const void *)d_ptr, ib, (const void *)vx,
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ib * QK8_0 + iqs + j, v);
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#ifdef GGML_SYCL_F16
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dfloat2 t1{y[col + j + 0], y[col + j + 1]};
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tmp += v * t1;
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#else
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tmp += v.x() * y[col + j + 0];
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tmp += v.y() * y[col + j + 1];
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#endif
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}
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}
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// reduce
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const int mask_start = ncols > GGML_SYCL_DMMV_X ? WARP_SIZE >> 1 : WARP_SIZE >> 2;
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for (int mask = mask_start; mask > 0; mask >>= 1) {
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tmp += dpct::permute_sub_group_by_xor(item_ct1.get_sub_group(), tmp, mask);
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}
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if (tid == 0) {
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#ifdef GGML_SYCL_F16
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dst[row] = tmp.x() + tmp.y();
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#else
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dst[row] = tmp;
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#endif
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}
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});
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}
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}
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static void dequantize_mul_mat_vec_q8_0_sycl(const void *vx, const dfloat *y,
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float *dst, const int ncols,
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const int nrows,
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@@ -1122,7 +1219,12 @@ void ggml_sycl_op_dequantize_mul_mat_vec(
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dequantize_mul_mat_vec_q5_1_sycl(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream);
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break;
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case GGML_TYPE_Q8_0:
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dequantize_mul_mat_vec_q8_0_sycl(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream);
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if ((ggml_tensor_extra_gpu *) dst->src[0]->extra &&
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((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) {
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dequantize_mul_mat_vec_q8_0_sycl_reorder(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream);
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} else {
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dequantize_mul_mat_vec_q8_0_sycl(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream);
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}
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break;
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case GGML_TYPE_Q2_K:
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dequantize_mul_mat_vec_q2_K_sycl(src0_dd_i, src1_ddf_i, dst_dd_i, ne00, row_diff, stream);
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